The present invention relates to microelectronic devices and their fabrication.
In ordinary semiconductor substrates, the active semiconductor region of a transistor is disposed in a well region of an oppositely doped bulk semiconductor region. In such structure, junction capacitance between the well and the bulk semiconductor region can impact performance. For increased performance, some microelectronic devices have active semiconductor regions in a silicon-on-insulator (“SOI”) layer of an SOI substrate. The SOI layer is separated from the main or “bulk” semiconductor region of the substrate by an insulating layer such as a buried oxide (“BOX”) layer or other dielectric layer. The insulating layer improves performance by eliminating junction capacitance between the SOI layer and the bulk semiconductor region.
However, SOI substrates are more complex than ordinary semiconductor substrates. More complex processing is required to form devices and to assure that they remain functional during use. In particular, SOI substrates require conductive vias to pass through the BOX layer and contact the bulk semiconductor region. In this way, the SOI substrate serves as a common node or ground node for devices. FIG. 1 illustrates a prior art contact structure in which a conductive via 10 extends through a stressed silicon nitride layer 12 and is electrically connected with a bulk semiconductor region 16 of an SOI substrate 20 through a polysilicon plug 14 covered with a silicide layer 44. As further shown in FIG. 1, another conductive via 50 is electrically connected to a semiconductor device, e.g., a field effect transistor 40 through a silicide layer 45 of its gate conductor. Both conductive vias extend through an interlevel dielectric layer 46 disposed above the device 40.
One drawback of the prior art contact structure is a number of processing steps which are needed only for the purpose of making the contact structure. To form the contact structure, an SOI substrate 20 (FIG. 2) having a trench isolation region 24 disposed therein and a nitride layer 22 thereon, is covered with a photoimageable layer 26, e.g., photoresist layer, which is then patterned to form an opening 28 within the boundaries of the trench isolation region 24 as shown in FIG. 2. As shown in FIG. 3, an opening 30 in the trench isolation region 24 and a BOX layer 18 of the substrate is patterned in accordance with the photoresist layer 26, such that the bulk semiconductor region 16 becomes exposed within the opening. As shown in FIG. 4, the photoresist is removed and then the opening in the trench isolation region 24 and the BOX layer 18 is filled with a layer of polysilicon 32 in contact with the bulk semiconductor region 16. The polysilicon fill 32 then is reduced in height and planarized to a major surface 34 of the trench isolation region 24 and the pad nitride layer 22 (FIG. 5). As illustrated in FIG. 6, the pad nitride layer then is removed and a device such as a field effect transistor 40 is formed which has a channel region 41 disposed within an active semiconductor region 42 of the substrate. Referring again to FIG. 1, regions 44, 45 of silicide then are formed atop the polysilicon plug 14 and atop a gate conductor of the FET 40, after which the interlevel dielectric layer 46 is formed. Conductive vias 10 and 50 then are formed which extend through the interlevel dielectric layer 46 and the stressed nitride layer 12 to contact the silicide layers 44, 45.
In such prior art method, the sole purpose of the processing described with respect to FIGS. 3, 4 and 5 is to form the polysilicon plug 14 that makes up part of the conductive structure contacting the bulk substrate region 16. It would be desirable to reduce the amount of processing required to form the conductive contact structure.